1. Field of the Invention
The present invention relates to a method of manufacturing a local interconnect. More particularly, the present invention relates to a method for simultaneously fabricating a gate conductive layer and a local interconnect.
2. Description of the Related Art
As the integration of integrated circuits is increased, the surface area of a chip available for forming interconnects becomes more and more limited due to the shrinking dimensions of devices. Because the number of interconnects required for electrical connection between devices or electrodes is increased, two or more conductive layers are designed to meet the requirements of high integration and limited surface area.
Local interconnect is an interconnect process used to improve the integration of semiconductor devices by locally connecting a gate and a source/drain region.
FIGS. 1A through 1D are schematic, cross-sectional diagrams used to depict steps in a conventional method for fabricating a local interconnect.
Referring to FIG. 1A, an isolation region 11 is formed in a provided substrate 10 to define active regions 20a, 20b. Patterned gate oxide layers 12a, 12b and patterned gate polysilicon layers 13a, 13b are formed in sequence in the active regions 20a, 20b, respectively. Also, source/drain regions 14a, 14b are formed in the active regions 20a, 20b, respectively. Spacers 15a, 15b are formed on the sidewall of the polysilicon layers 13a, 13b.
Referring to FIG. 1B, a self-aligned silicide process is performed, thus silicide layers 16a, 16b, 17a and 17b are formed on the source/drain region 14a, 14b and the gate polysilicon layer 13a, 13b, respectively. The material used to form the silicide layer is titanium silicon.
Referring to FIG. 1C, a titanium nitride layer 18 is formed over the substrate 10. A patterned photoresist layer 19 is formed on the titanium layer 18 to define a region of a subsequently formed local interconnect.
Referring to FIG. 1D, a portion of the titanium nitride layer 18 exposed by the photoresist layer 19 is removed by etching. Then, the photoresist layer 19 is removed. A titanium nitride layer 18a is formed as a local interconnect.
The silicide layer, which can reduce the sheet resistance of the gate polysilicon layer and the source/drain region, is formed by performing the self-aligned silicide process. Then, the titanium nitride layer 18a is formed as a local interconnect to connect the source/drain region 14b and the gate polysilicon layer 13b through the silicide layer 16b and 17b. However, as the linewidth of the gate is reduced, a narrow linewidth effect occurs. Thus, the sheet resistance is increased, the conductivity of the silicide layer and the performance of devices are reduced.